The present invention generally relates to an adder-subtracter circuit with bypass capability which can feed back the result to itself and is used for example in processors and more specifically in digital signal processors, and methods related thereto and used therewith.
The circuit usually is arranged in the data path and can perform adds and subtracts and can bypass the result to itself. The purpose of the bypassing operation can be to adjust the frequency of instruction executions. Especially the frequency of instruction executions can be adjusted to be equal to the frequency of the surrounding components of the processor in which the circuit is used.
One known circuit is depicted in FIG. 3. The known circuit includes a prefix type adder 24 of n bit, n in the described example being 4. The adder 24 for each bit has two n bit inputs a, b and two outputs p, g. The respective output pairs p[0]-g[0], p[1]-g[1], p[2]-g[2] and p[3]-g[3] of each bit are directed to a respective result XOR gate 23 which generates for each bit the result. In the following the bit position is indicated in brackets following the reference. If reference is made to several bit positions then the range of the corresponding bit positions is indicated in brackets. So the plurality of the result XOR gates 23[0], 23[1], 23[2], and 23[3] can be referenced as 23[3:0] and generate the n bit result r[3:0].
The circuit comprises for each bit a first input line d1 and a second input line d2 for inputting a respective bit of a first n bit operand and a second n bit operand respectively. The adder receives the first operand via the input lines d1[0], d1[1], d1[2] and d1[3] directly at the input a. The second operand is directed to one of two n bit inputs of a n bit selector 19. At the other input the selector 19 receives the output r[3:0] of the result XOR gates 23. The selector 19 is controlled by an input line instr_bypass and dependent on the state of this signal forwards the second operand or the result to the output of the selector. The single bits of output signal of the selector are received by first inputs of a plurality of subtract XOR gates 20[3:0] each comprising two inputs. The second inputs of the subtract XOR gates 20[3:0] are receiving an inverted subtract signal instr_sub. Dependent on the state of the subtract signal instr_sub the subtract XOR gates 20[3:0] invert the bits of the output of the selector 19 or not. The result is that the subtract signal instr_sub controls whether the output of the selector 19 is added to or subtracted from the first operand.
Furthermore the circuit comprises a carry_in input line through which a carry bit from a further adder-subtracter circuit can be inputted in order to cascade multiple adder-subtracter circuits. The input line carry_in would receive a carry_out signal of an adder-subtracter circuit processing next less significant bits. In the same way the adder 24 can output a carry_out signal for a further adder-subtracter circuit processing the next more significant bits.
The adder 24 used in the circuit generates its output signals p[3:0] and g[3:0] from it's input signals a[3:0] and b[3:0] by a network of logic gates, the generation of the signals p[3:0] requiring in most cases less gate stages and therefore a smaller time delay than the generation of the signals g[3:0]. Furthermore the external result XOR gates 23[3:0] and the subtract XOR gates 20[3:0] add to the critical path corresponding to the most time consuming data path.
This circuit has the disadvantage that the critical path comprises many gates and therefore reduces the maximum frequency of instruction executions.
The present invention solves the aforementioned exemplary problems, and/or other problems in the art, and provides an adder-subtracter circuit with a reduced number of gates in the critical path and therefore increased maximum frequency of instruction executions.